void ar7240_gpio_config(void)
{
/* Disable clock obs
* clk_obs1(gpio13/bit8), clk_obs2(gpio14/bit9), clk_obs3(gpio15/bit10),
* clk_obs4(gpio16/bit11), clk_obs5(gpio17/bit12)
* clk_obs0(gpio1/bit19), 6(gpio11/bit20)
*/
ar7240_reg_wr (AR7240_GPIO_FUNC,
(ar7240_reg_rd(AR7240_GPIO_FUNC) & ~((0x1f<<8)|(0x3<<19))));
/* Enable eth Switch LEDs */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | (0x1f<<3)));
/* Clear AR7240_GPIO_FUNC BIT2 to ensure that software can control LED5(GPIO16) and LED6(GPIO17) */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~(0x1<<2)));
/* Set HORNET_BOOTSTRAP_STATUS BIT18 to ensure that software can control GPIO26 and GPIO27 */
ar7240_reg_wr (HORNET_BOOTSTRAP_STATUS, (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) | (0x1<<18)));
/* Disable EJTAG functionality to enable GPIO 8, added by zcf, 20110608 */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | 0x01));
#ifdef CONFIG_PID_MR302001
/* set OE, added by zcf, 20110509 */
ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xc020001));
/* Disable clock obs, added by zcf, 20110509 */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f));
#endif
#ifdef CONFIG_PID_WR74104
/* set OE, added by zcf, 20110509 */
ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xc03e001));
/* Disable clock obs, added by zcf, 20110509 */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e007));
#endif
#ifdef CONFIG_PID_WR74302CN
/* set OE, added by zcf, 20110714 */
ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xc03e003));
/* Disable clock obs, added by zcf, 20110509 */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e007));
#endif
#ifdef CONFIG_PID_MR322002
/* set OE, added by zcf, 20110714 */
ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xc03e001));
/* Disable clock obs, added by zcf, 20110509 */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e007));
#endif
#ifdef CONFIG_PID_WR70301
/* set OE, added by zcf, 20110714 */
ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xc03e001));
#endif
#ifdef CONFIG_PID_MR11U01
/* set OE, added by zml, 20111018 */
ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xc020001));
/* Disable clock obs, added by zml, 20111018 */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f));
#endif
}
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